Engineering Jobs at Citadel Securities
7 open engineering roles · median $56k
Open Engineering roles
7
Median pay
$56k
Top seniority
INTERN
7 of 7 roles
Remote-friendly
0%
0 of 7 are remote
Open Engineering roles at Citadel Securities
Showing 7 of 7| Role | Location | Salary | Activity | |
|---|---|---|---|---|
2026-2027 FPGA Engineer Internship | Sydney NSW, Australia | Salary not listed | Posted today | View→ |
2026-2027 FPGA Engineer Internship | Sydney NSW, Australia | Salary not listed | Posted today | View→ |
2026-2027 FPGA Engineer Internship | Sydney NSW, Australia | Salary not listed | Posted today | View→ |
2026-2027 FPGA Engineer Internship | Sydney NSW, Australia | Salary not listed | Posted today | View→ |
2026-2027 FPGA Engineer Internship | Sydney NSW, Australia | $49k - $62k | Posted today | View→ |
2026-2027 FPGA Engineer Internship | Sydney NSW, Australia | Salary not listed | Posted today | View→ |
2026-2027 FPGA Engineer Internship | Sydney NSW, Australia | Salary not listed | Posted today | View→ |
Seniority mix
7 classified roles- INTERN 7 (100%)
Where the roles are
Top locationsWork model
7 roles classified- Onsite 7 (100%)
Tech stack signals
Mentioned across Engineering descriptionsFPGA 7Python 7SystemVerilog 7C 7Bash 7VHDL 7Tcl 7RTL 1
Salary by seniority
Engineering roles only| Seniority | Avg min | Avg max | Roles |
|---|---|---|---|
| INTERN | $49k | $62k | 1 |