Engineering Jobs at Celero Communications
26 open engineering roles · median $210k
Open Engineering roles
26
of 28 total at Celero Communications
Median pay
$210k
Top seniority
PRINCIPAL
23 of 26 roles
Remote-friendly
0%
0 of 4 are remote
Open Engineering roles at Celero Communications
Showing 26 of 26| Role | Location | Salary | Activity | |
|---|---|---|---|---|
Principal SerDes Design Engineer | Ottawa, Ontario, Canada | $120k - $157k | Posted today | View→ |
Principal PLL Design Engineer | Vancouver, British Columbia, Canada | $120k - $157k | Posted today | View→ |
Principal SerDes Design Engineer | Irvine, California, United States | $205k - $265k | Posted today | View→ |
Principal PLL Design Engineer | Ottawa, Ontario, Canada | $117k - $150k | Posted today | View→ |
Principal SerDes Design Engineer | Vancouver, British Columbia, Canada | $135k - $175k | Posted today | View→ |
Principal PLL Design Engineer | Irvine, California, United States | $195k - $250k | Posted today | View→ |
Principal PLL Design Engineer | San Jose, California, United States | $215k - $265k | Posted today | View→ |
Principal Analog Design Engineer | Ottawa, Ontario, Canada | $117k - $153k | Posted today | View→ |
Principal SerDes Design Engineer | San Jose, California, United States | $215k - $265k | Posted today | View→ |
Principal Analog Design Engineer | San Jose, California, United States | $205k - $265k | Posted today | View→ |
Principal Analog Design Engineer | Irvine, California, United States | Salary not listed | Posted today | View→ |
Principal Analog Design Engineer | Vancouver, British Columbia, Canada | Salary not listed | Posted today | View→ |
Design Validation & Test (DVT) Engineer | Irvine, California, United States | $175k - $225k | Posted 3d ago | View→ |
Coherent DSP Applications Engineer | Irvine, California, United States | $185k - $235k | Posted 3d ago | View→ |
Coherent DSP Applications Engineer | San Jose, California, United States | $195k - $245k | Posted 3d ago | View→ |
Principal Physical Verification Engineer | Irvine, California, United States | $185k - $230k | Posted 5d ago | View→ |
Principal Design-for-Test (DFT) Engineer | Irvine, California, United States | $195k - $245k | Posted 5d ago | View→ |
Principal Physical Verification Engineer | San Jose, California, United States | $205k - $255k | Posted 5d ago | View→ |
Principal Analog Layout Design Engineer/Lead | Ottawa, Ontario, Canada | $106k - $135k | Posted 5d ago | View→ |
Principal Physical Design Engineer | San Jose, California, United States | $205k - $265k | Posted 5d ago | View→ |
Principal Analog Layout Design Engineer/Lead | Irvine, California, United States | $185k - $235k | Posted 5d ago | View→ |
Principal Physical Design Engineer | Irvine, California, United States | $205k - $260k | Posted 5d ago | View→ |
Principal Analog Layout Design Engineer/Lead | San Jose, California, United States | $195k - $255k | Posted 5d ago | View→ |
DSP - FEC Design Engineer | Ottawa, Ontario, Canada | $77k - $99k | Posted 6d ago | View→ |
DSP - FEC Design Engineer | Vancouver, British Columbia, Canada | $77k - $99k | Posted 6d ago | View→ |
DSP - Optical Design Engineer | Vancouver, British Columbia, Canada | $77k - $99k | Posted 6d ago | View→ |
Seniority mix
26 classified roles- PRINCIPAL 23 (88%)
- MID 3 (12%)
Where the roles are
Top locationsWork model
4 roles classified- Onsite 4 (100%)
Tech stack signals
Mentioned across Engineering descriptionsPython 14MATLAB 12CMOS 10HFSS 8Spectre 8EMX 8PLL 7SerDes 7Cadence Virtuoso 7FinFET 6SystemVerilog 5Calibre 5Tcl 5ADE 4Verilog A 4
Salary by seniority
Engineering roles only| Seniority | Avg min | Avg max | Roles |
|---|---|---|---|
| PRINCIPAL | $175k | $223k | 21 |
| MID | $77k | $99k | 3 |