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APPLE INC has the following available in Beaverton, Oregon. Collaborating with all disciplines (vertical product model). Ensuring the quality of the SOC or an IP or subsystem. Reviewing design and architecture specifications and working closely with design \u0026 micro-architecture teams. Understanding the functional and performance goals of the design and use this knowledge to test effectively. Developing test plans, tests \u0026 coverage plans as well as define Apple’s next generation verification methodology \u0026 test benches. Communicating and collaborating with design, architecture and software to understand the use cases and corner conditions and driving test cases. Running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results. 40 hours/week.
Master’s Degree or foreign equivalent in Computer Engineering, Electrical Engineering or related field.\\nExperience and/or education must include:\\n\\nUtilizing System Verilog and UVM framework to write test bench code\\nCreating test plans using constrained random verification (CRV) or directed testing to verify ASICs\\nUtilizing C to write microprocessor tests for ASIC/Embedded tests.\\nReviewing design and architecture specifications and working closely with design and micro-architecture teams to understand functional and performance goals\\nDeveloping test coverage plan, collecting test bench coverage, and resolving coverage gaps in ASIC test suite\\nImplementing IP block test environments and test cases for ASICs\\nUtilizing Xcelium, Questa, or VCS to analyze simulation failures\\nProgramming scripts in Python or Perl to automate test bench analysis
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APPLE INC has the following available in Beaverton, Oregon. Collaborating with all disciplines (vertical product model). Ensuring the quality of the SOC or an IP or subsystem. Reviewing design and architecture specifications and working closely with design \u0026 micro-architecture teams. Understanding the functional and performance goals of the design and use this knowledge to test effectively. Developing test plans, tests \u0026 coverage plans as well as define Apple’s next generation verification methodology \u0026 test benches. Communicating and collaborating with design, architecture and software to understand the use cases and corner conditions and driving test cases. Running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results. 40 hours/week.
Master’s Degree or foreign equivalent in Computer Engineering, Electrical Engineering or related field.\\nExperience and/or education must include:\\n\\nUtilizing System Verilog and UVM framework to write test bench code\\nCreating test plans using constrained random verification (CRV) or directed testing to verify ASICs\\nUtilizing C to write microprocessor tests for ASIC/Embedded tests.\\nReviewing design and architecture specifications and working closely with design and micro-architecture teams to understand functional and performance goals\\nDeveloping test coverage plan, collecting test bench coverage, and resolving coverage gaps in ASIC test suite\\nImplementing IP block test environments and test cases for ASICs\\nUtilizing Xcelium, Questa, or VCS to analyze simulation failures\\nProgramming scripts in Python or Perl to automate test bench analysis
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