Greetings,

Position: DESIGN VERIFICATION ENGINEER
Location: On-Site at Sunnyvale, CA
Contract: C2C/W2
End Client: Google, Facebook, Cisco, Intel
Implemented by: HCL

Requirements:
Building a test bench for a block using System Verilog and UVM
Writing random tests, directed tests, error tests & performance tests for a block of Verilog and UVM.
Developing, maintaining and supporting of the UVM verification environment.
Debugging tests with design engineers to deliver functionally correct design blocks
writing & analyzing functional coverage, assertions
Generating and analyzing code coverage & writing waivers

[You can reply to this email with an Updated Resume and details of your Work Authorization if you're interested in working for this position. For further information, feel free to reach out to me.]